FPGA/ASIC Design Engineer (Silicon Engineering)
Core
Designing and optimizing ASICs and FPGAs for Starlink satellite and ground infrastructure to enable global broadband connectivity.
Role type
FPGA/ASIC Design Engineer (Silicon Engineering)
Builds
Next-generation FPGAs and ASICs for Starlink satellites and ground systems
Domain
Aerospace / Satellite Communications / Hardware Design
Deliverable
production ML models | product features | infrastructure
Required skills
RTL Design (SystemVerilog, Verilog, VHDL), SoC block design and integration, Power/Performance/Area (PPA) optimization, AXI/AHB/APB protocols, EDA tools (VCS, Questa, Vivado, Quartus), PCB debugging with oscilloscopes and spectrum analyzers
Preferred skills
ASIC/FPGA system integration, Python/C/C++/Bash scripting, DSP and digital communication datapath design, Modem design
Technologies
SystemVerilog, Verilog, VHDL, VCS, Questa, Xilinx Vivado, Altera Quartus II, AXI, AHB, APB
Responsibilities
Design ASICs and/or FPGAs implementing complex SoC blocks; Optimize designs for power, performance, and area; Participate in the full design lifecycle from architecture to validation; Build tools to analyze on-orbit and lab data; Engage in high-level architectural design for test systems; Collaborate on production software development
Seniority
Mid-level IC Engineer