Lead Design Engineer
Core
Lead Design Engineer for Advanced Physical IP Development, focusing on high-performance Consumer PHYs and industry-standard protocols.
Role type
Senior IC Design Engineer (Physical IP)
Builds
High-performance physical IP for industry-standard protocols (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA)
Domain
Semiconductor / Electronic Design Automation / High-speed Serial Interfaces
Deliverable
production ML models | product features
Required skills
ASIC design, RTL design/verification, Design Architecture, Micro-architecture, Synthesis, Constraint generation, Power management, DFT, Low-power design, FPGA testing, System Verilog, Python, C/C++, Analog Mixed-Signal basics, SI/PI, Post-Silicon Validation
Preferred skills
High-speed serial interface link IPs in advanced technology nodes, Embedded microcontroller/DSP usage, Firmware development, Cadence ASIC design tools
Technologies
System Verilog, Python, C/C++, Cadence ASIC design tools, FPGA, Palladium
Responsibilities
Drive architecture to micro-architecture to RTL implementation; Specify coverage points, testing strategy, corner conditions, and stimulus creation; Partner with cross-functional teams (Analog, Layout, Backend, Firmware, Validation) to complete IP deliverables; Integrate IPs into subsystems and support customer releases
Seniority
Senior, hands-on IC
