Lead Software Engineer - Low-Power Verification
Core
Lead Software Engineer improving UPF compilation performance and correctness for multi-billion-gate low-power designs on Palladium and Protium emulation platforms.
Role type
Senior IC software engineer (verification tooling)
Builds
UPF compilation flows (Parallel Partition Compiler, Modular Compiler) and documentation for emulation/prototyping platforms
Domain
Semiconductor EDA, low-power verification, emulation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UPF (IEEE 1801), SystemVerilog, Verilog, VHDL, C++, Perl, Tcl/Tk, Python, technical writing
Preferred skills
AI-assisted coding tools fluency, object-oriented design reasoning
Technologies
Palladium, Protium, UPF, SystemVerilog, C++, Perl, Tcl/Tk, Python
Responsibilities
Improve UPF compilation performance and add self-checks across compiler flows; Rebuild UPF documentation with valid examples; Collaborate with R&D/PE/AE teams to deploy UPF solutions; Consolidate UPF compilation across platforms
Seniority
Senior, hands-on IC
