Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions
Core
Lead advanced signoff methodology development, customer enablement, and product deployment for timing signoff and ECO solutions in semiconductor design.
Role type
Senior Principal Product Engineer (Silicon Signoff Verification & Digital Implementation)
Builds
Production signoff methodologies, timing closure flows, and ECO convergence solutions for advanced-node ASIC/SoC designs.
Domain
Semiconductor / Physical Design / Signoff
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Static Timing Analysis (STA), Multi-mode multi-corner (MMMC) timing analysis, Signoff methodologies, Statistical timing analysis, Signal Integrity and Crosstalk Analysis, Glitch analysis and fixing, ECO implementation and closure, Timing correlation, Power optimization, RC extraction, Physical implementation optimization
Preferred skills
Advanced-node technology support (7nm/5nm/3nm/2nm), Large SoC design closure (>100M instances), PPA optimization, AI-assisted design closure workflows
Technologies
Cadence Tempus/PrimeTime, Cadence Innovus/ICC/FC, Tempus ECO/Tweaker
Responsibilities
Drive development and deployment of advanced signoff methodologies for timing, power, and signal integrity; Collaborate with customers and R&D to resolve complex design closure challenges; Lead qualification and certification for advanced-node design flows; Support customer tapeouts through root-cause analysis and debug; Create deployment collateral and technical presentations; Drive adoption of emerging technologies like AI-assisted signoff
Seniority
Senior, hands-on IC with strategic customer leadership
