Principal Design Engineer
Core
Leading physical design, timing closure, and verification for complex IP and SoC designs below 7nm.
Role type
Principal Design Engineer (Physical Design)
Builds
Complex IP blocks and System-on-Chip (SoC) designs
Domain
Semiconductor / ASIC Design / Deep Sub-Micron Technology
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
hierarchical physical design strategies, timing closure, physical verification, formal verification, EM-IR analysis, deep sub-micron technology knowledge, Cadence implementation tools (Genus, Innovus, Quantus, Tempus, PVS, Voltus), automation scripting (Makefile, Tcl, Tk, Perl, Python)
Preferred skills
AI experience
Responsibilities
Execute physical design flow for complex SoCs, ensure timing closure, perform physical verification, develop automation scripts for design flow optimization, mentor team members on deep sub-micron design challenges
Seniority
Senior, hands-on IC