Principal DFT Engineer
Core
Design for Test (DFT) engineering for SoC/ASIC digital designs, focusing on test insertion, pattern generation, and fault coverage analysis.
Role type
Principal DFT Engineer
Builds
Testable silicon designs with high fault coverage
Domain
Semiconductor / SoC/ASIC Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT insertion flows, scan chain insertion, compression scan insertion, LBIST, memory built-in self-test (MBIST), Automatic Test Pattern Generation (ATPG), JTAG 1149.1/6, IEEE1500, IEEE1687, timing analysis, equivalency checks
Preferred skills
Cadence tools and flows, timing analysis, equivalency checks
Technologies
Synthesis tools, ATPG tools, JTAG, IEEE1500, IEEE1687
Responsibilities
Insert DFT flows including scan chains, compression scan, and LBIST; Develop and verify ATPG testbenches to achieve coverage goals; Debug and analyze test failures to improve fault coverage; Perform timing analysis and equivalency checks.
Seniority
Senior, hands-on IC
