DFT Design Engineer
Core
Design for Test (DFT) engineering for SoC/ASIC digital designs, focusing on scan chain insertion, memory testing, and automatic test pattern generation.
Role type
DFT Design Engineer
Builds
Testable SoC/ASIC chips with high fault coverage
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
scan chain insertion, compression scan technologies, memory built-in self-test (MBIST), automatic test pattern generation (ATPG), JTAG 1149.1/6, IEEE1500, IEEE1687, timing analysis, equivalency checks
Preferred skills
synthesis, verification, debugging Verilog testbenches, Cadence tools and flows
Technologies
Verilog, Cadence tools
Responsibilities
Insert scan chains and compression scan technologies, generate ATPG patterns to achieve test coverage goals, debug and analyze failures to improve fault coverage, verify ATPG testbenches and debug simulation mis-compares
Seniority
Mid-Senior, hands-on IC
