Sr Principal Design Engineer
Core
Designing physical IP for industry-standard high-speed serial-links, covering mixed-signal circuit design, verification, and testing.
Role type
Sr Principal Design Engineer (Mixed-Signal)
Builds
Physical IP for high-speed serial-links
Domain
Semiconductor / Analog & Mixed-Signal Design
Deliverable
production ML models | product features | infrastructure
Required skills
Mixed-signal circuit design fundamentals, Mixed-signal circuit design and verification flows, Cadence analog design environment, Signal processing concepts
Preferred skills
Serial link design techniques, Data converter (ADC/DAC) design, Clock synthesis and recovery (PLLs/DLLs/CDRs), MATLAB or C for architecture, Hardware description languages (SystemVerilog/VerilogA), Scripting (Perl/Python), Silicon validation testing
Technologies
Cadence, SystemVerilog, VerilogA, MATLAB, C, Perl, Python
Responsibilities
Develop circuit design from high-level architectural specifications, Create and execute post-silicon test plans, Collaborate with digital teams for functional and performance closure
Seniority
Sr Principal, hands-on IC with project leadership