Lead Design Engineer
Core
Lead verification strategy, architecture, and execution for semiconductor/ASIC/SoC designs, ensuring functional and timing sign-off.
Role type
Senior IC Digital Verification Engineer (DV)
Builds
Verification environments, testbenches, and validation artifacts for chip designs
Domain
Semiconductor / ASIC / SoC / Digital Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, SystemVerilog, Bus Functional Models (BFMs), monitors, scoreboards, checkers, Constraint Random Testing, Formal Verification, Debugging, Root-cause analysis, Coverage analysis, Gate-Level Simulation (GLS)
Preferred skills
Mentorship, Cross-functional collaboration, Project management
Technologies
UVM, SystemVerilog, Formal tools, Simulation environments
Responsibilities
Define verification strategy and methodology; Design scalable verification environments and testbenches; Write complex test cases and sequences; Lead root-cause analysis of design bugs; Implement constrained-random stimulus generation; Utilize formal verification tools; Monitor and analyze coverage metrics; Oversee Gate-Level Simulation; Provide final technical approval for verification phase.
Seniority
Senior, hands-on IC
