Sr. Principal Design Engineer
Core
Lead verification strategy and execution for complex IP, Subsystem, and SOC/Chiplet based designs, ensuring coverage-driven closure.
Role type
Sr. Principal Design Engineer (Verification)
Builds
Production-ready verification environments, test plans, and functional models for complex SoCs and Chiplet architectures.
Domain
Semiconductor / VLSI / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> production verification environments and test plans
Required skills
UVM methodology, SystemVerilog, SOC level verification, coverage-driven verification, bus functional modeling, debug and problem solving
Preferred skills
SOC level verification experience, Chiplet based SOC experience
Technologies
UVM, SystemVerilog
Responsibilities
Develop test plans, tests, and verification environments using UVM methodology; Create bus functional models, monitors, checkers, and scoreboards; Lead verification strategy and high quality execution for SOCs/Chiplet based SOCs; Mentor and guide verification engineers to foster technical excellence.
Seniority
Sr. Principal, hands-on IC with mentorship
