Design Verification Engineer- Senior / Principal
Core
Lead verification of complex CPU or SoC IP designs to ensure premium-quality, high-performance silicon delivery.
Role type
Senior/Principal Design Verification Engineer (SoC/CPU)
Builds
Custom IP and System-on-Chip (SoC) designs
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, C++, Verilog debugging, simulation/emulation environments, Python/Perl scripting, coverage-based verification, random-stimulus generation, test plan development, bug debugging, mentorship
Technologies
UVM, C++, Verilog, Python, Perl
Responsibilities
Plan verification for complex design IP/SoC interacting with architecture and design engineers; Develop verification environments and run/debug simulations; Apply random-stimulus and coverage-based techniques to find bugs; Coach and mentor others in verification expertise.
Seniority
Senior/Principal, hands-on IC with mentorship
