Software Engineer II
Core
Develop Formal Verification IPs using Verilog design models and System Verilog Assertions for industry standard bus protocols.
Role type
IC RTL Design and Verification Engineer
Builds
Formal Verification IPs and verification environments
Domain
Electronic Design Automation (EDA) / Semiconductor
Deliverable
production ML models | product features
Required skills
Verilog, System Verilog Assertions, industry standard bus protocols (AHB, AXI, CHI, PCIe), RTL design, synthesis concepts, verification environment setup, test plan creation, coverage analysis, Python/TCL scripting, EDA tools debugging
Preferred skills
Formal verification, AI tools for verification/automation/debugging, flow development
Technologies
Verilog, System Verilog, Python, TCL, AHB, AXI, CHI, PCIe, Cadence EDA tools
Responsibilities
Develop Assertion Based Verification IPs, understand designs and assertions for formal verification, automate verification tasks using scripting languages, coordinate with cross-functional teams, debug design and verification problems using EDA tools
Seniority
Mid-level IC Engineer
