Sr Principal Design Engineer
Core
Lead physical design implementation projects for low power and high speed ASICs at deep sub-micron nodes, including floor planning, P&R, timing closure, and signoff.
Role type
Senior IC physical design engineer (ASIC)
Builds
ASIC chips for customers
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
hierarchical physical design strategies, deep sub-micron technology knowledge, low power design, DFT, static timing analysis, clock tree synthesis, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM closure
Preferred skills
next generation physical design methodology development, formal verification
Technologies
Cadence tools, ASIC design flow
Responsibilities
Perform physical design implementation (floor planning, place and route, timing closure), lead flow development, collaborate with RTL teams for tapeout success
Seniority
Senior, hands-on IC
