Principal Design Engineer
Core
Architect, design, and deliver high-speed analog/mixed-signal circuits for Die-to-Die and chiplet-based systems, specifically focusing on UCIe-compliant interfaces.
Role type
Principal Analog Design Engineer (High-Speed Interfaces)
Builds
High-speed interface IPs (UCIe, D2D) for advanced packaging technologies
Domain
Semiconductor IC Design / High-Speed Analog / Advanced Packaging
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal IC design, high-speed interface design (DDR, PCIe, SerDes), UCIe standard concepts, advanced packaging integration, schematic-level design, simulation across PVT corners, signal integrity analysis, clocking, noise analysis
Preferred skills
UCIe PHY design, AMS verification flows, post-silicon debug, power integrity, thermal considerations, technical mentorship
Technologies
EDA tools, UCIe standard, 2.5D/3D packaging, interposers, organic substrates
Responsibilities
Architect and design high-speed analog blocks (clocking, TX/RX, termination, equalization), perform feasibility analysis and design trade-offs, execute schematic design and simulation, co-optimize circuit and package design, support layout reviews and post-layout sign-off, collaborate on full-chip integration, participate in silicon bring-up and debug, contribute to design methodologies
Seniority
Principal, hands-on IC design with architectural ownership
