Principal Design Engineer
Core
Architect, design, and deliver high-speed Analog/Mixed-Signal IPs and subsystems for next-generation connectivity and memory interfaces.
Role type
Principal Analog Circuit Design Engineer (High-Speed Interfaces)
Builds
UCIe, D2D, PCIe, DDR/LPDDR, HBM, GDDR, and SerDes IPs on advanced technology nodes
Domain
Semiconductor / Analog Circuit Design / High-Speed Interfaces
Deliverable
production ML models | product features
Required skills
High-speed interface design (UCIe, D2D, PCIe, DDRx, HBM, SerDes), Analog Design and I/O fundamentals, SI/PI, ESD, Reliability, Jitter, Timing, PPA optimization, Cross-functional team leadership, Complex IP program management
Preferred skills
Advanced technology nodes (16nm to 3nm), IP architecture and technology migration, Design reuse methodologies, Leading large technical teams
Technologies
UCIe, PCIe Gen3/4/5/6, DDRx, LPDDRx, GDDRx, HBM, SerDes, 16nm, 12nm, 10nm, 7nm, 5nm, 3nm
Responsibilities
Architect and design high-speed Analog/Mixed-Signal IPs, Drive design closure for TX/RX, PLL, DLL, CDR, Clocking, Datapath, I/O, and interface circuits, Lead complex IP programs with cross-functional teams, Mentor engineers and drive technical excellence, Lead project execution, staffing, risk management, and customer engagements
Seniority
Principal, hands-on IC with leadership