Sr Principal Design Engineer
Core
Lead VLSI design verification engineering for complex chip designs, ensuring functional correctness through advanced verification methodologies and automation.
Role type
Sr Principal Design Engineer (VLSI Verification)
Builds
Production-ready integrated circuits and semiconductor chips
Domain
Semiconductor / VLSI / Hardware Design
Deliverable
production ML models | product features
Required skills
VLSI domain expertise, Verilog, HVL (SV, Specman e), UVM/OVM/eRM methodology, assertions development, constraint randomization, functional and code coverages, formal verification, test-bench development, RTL and GLS simulation debug, Perl/Tcl scripting, project management
Technologies
Verilog, Specman e, UVM, OVM, eRM, Perl, Tcl
Responsibilities
Develop and maintain complex verification environments using UVM/OVM/eRM; Create and close assertions and implement constraint randomization strategies; Perform formal verification and analyze coverage metrics; Debug RTL and GLS simulations; Manage project schedules and deliver verification results independently; Automate verification tasks using Perl/Tcl scripting.
Seniority
Senior, hands-on IC
