ASIC Verification Engineer
Core
Design, analyze, develop, and verify VLSI components and hardware systems, specifically focusing on ASIC verification environments and tape-out readiness.
Role type
ASIC Verification Engineer
Builds
Block-level, subsystem, and full-chip verification environments for complex integrated circuits
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, constrained-random verification, Perl/Tcl/Python/Shell scripting, front-end simulators (VCS/NC), debugging, functional coverage analysis
Preferred skills
Ethernet protocol verification
Technologies
SystemVerilog, UVM, VCS, NC, Perl, Python, Shell, Tcl
Responsibilities
Develop and enhance ASIC verification environments; Architect and build verification environments; Define and execute verification suites; Verify large ASIC blocks and drive tape-out readiness; Collaborate with logic designers to debug design issues; Develop automation scripts for verification infrastructure
Seniority
Mid-level, independent contributor
