ASIC Verification Engineer
Core
Design, analyze, develop, and evaluate VLSI components and hardware systems, focusing on architecture, logic design, and design verification through software simulation.
Role type
ASIC Verification Engineer
Builds
Block-level, subsystem, and full-chip verification environments for complex ASICs
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments)
Required skills
SystemVerilog, UVM (Unified Verification Methodology), constrained-random verification, Perl/Tcl/Python/Shell scripting, front-end simulators (VCS, NC), debugging complex ASIC blocks
Preferred skills
Ethernet protocol verification
Technologies
SystemVerilog, UVM, VCS, NC, Perl, Tcl, Python, Shell
Responsibilities
Develop and enhance ASIC verification environments; Architect and build verification environments; Define and execute verification suites and test cases; Verify large ASIC blocks and drive tape-out readiness; Collaborate with logic designers to debug design issues; Develop automation scripts for verification infrastructure
Seniority
Mid-level IC engineer (3+ years experience)
