Lead Design Engineer
Core
Develop and integrate foundry rule decks and technology files to support Process Design Kits (PDKs), ensuring physical verification and automation of design flows.
Role type
Lead Design Engineer (Physical Verification & PDK Development)
Builds
PDKs, verification rule decks, and automated design flows for semiconductor manufacturing
Domain
Semiconductor / IC Design / Physical Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
PDK development, physical verification methodology, automation scripting (Python, SKILL, Perl), deep sub-micron CMOS process knowledge, Cadence Virtuoso platform, Pcell creation, DRC/LVS/Parasitic Extraction flows, revision control
Preferred skills
Cadence PVS, Assura, layout design, device physics
Technologies
Cadence Virtuoso, Python, SKILL, Perl, Git, Subversion, Synchronicity, PVS, Assura
Responsibilities
Develop and integrate foundry rule decks and technology files; automate LVS, DRC, RM, IR, and Parasitic Extraction flows; support layout teams in verification flow issues; ensure QA of integrated PDKs with custom design environments; interface with design and foundry teams to develop and verify PDKs; maintain automation frameworks for efficiency improvement
Seniority
Senior, hands-on IC
