Senior Engineer, Digital Verification
Core
Lead verification planning and execution for complex digital and mixed-signal IC designs, architecting advanced verification environments and driving silicon bring-up.
Role type
Senior IC design verification engineer (digital/mixed-signal)
Builds
Verification environments and test strategies for mixed-signal products
Domain
Semiconductor / Mixed-signal IC design
Required skills
SystemVerilog, UVM, Mixed-signal verification, Constrained random verification, Assertion-based verification, Debugging complex designs, Verification planning, Scripting (Python, Perl, TCL), Technical mentorship
Preferred skills
Master's degree in EE/CE, 4-8 years experience in digital/mixed-signal IC verification
Technologies
SystemVerilog, UVM, Python, Perl, TCL
Responsibilities
Architect comprehensive verification strategies, Develop advanced UVM-based verification environments, Establish verification metrics and coverage goals, Lead debug efforts for complex design issues, Provide technical guidance to junior engineers, Collaborate with design teams on verification planning, Lead silicon bring-up and post-silicon validation
Seniority
Senior, hands-on IC
