Staff STA Engineer
Core
Lead Synthesis & Static Timing Analysis (STA) for complex high-performance ICs with large digital & analog interfaces.
Role type
Staff Synthesis & STA Engineer
Builds
High-performance digital blocks and SoCs
Domain
Semiconductor / Digital IC Design
Required skills
Digital Synthesis, DFT insertion, Check Design, Check Timing Analysis, Liberty models, Timing constraints, LEC, PD tools, Timing ECOs, Scan/DFT modes, Leakage/Dynamic power optimization, RTL to GDS flow, TCL/Perl/Python automation, Floor-planning, Placement, CTS, Routing, Extraction, Physical Verification, EM/IR flows
Preferred skills
Physical design tools expertise
Technologies
Synthesis tools, STA tools, LEC tools, PD tools, TCL, Perl, Python
Responsibilities
Digital Synthesis of high performance Digital blocks, Timing constraint development, analysis, validation and debug, RTL to Netlist Logical equivalence check and debugging failures, STA flow setup, convergence, reviews, flow optimization, Timing, Noise, DRC signoff for multi-mode, multi-corner, Flow automation using scripts, Supporting Floor-planning, Placement, CTS, Routing, Extraction, Physical Verification, EM/IR flows, Signoff checks
Seniority
Staff, hands-on IC
