Digital Design Engineer, DFT
Citizens or permanent residents only
Core
Designing and implementing Digital Design for Test (DFT) architectures, scan patterns, and verification strategies for ASIC/SoC products.
Role type
Senior IC Digital Design Engineer (DFT)
Builds
ASIC/SoC chips with embedded DFT infrastructure
Domain
Semiconductor / Digital Design
Required skills
DFT architecture and planning, scan insertion, ATPG, DFT compression, on-chip clock control, gate-level simulation, failure analysis, Perl/Python/Tcl scripting
Preferred skills
Tessent DFT tools, IEEE 1149 and JTAG, LBIST and MBIST, low power DFT, SSN, fault grading
Technologies
Perl, Python, Tcl, Tessent, ATPG tools
Responsibilities
Define DFT specifications and architecture, support DFT insertion across product lines, develop high coverage/low power scan patterns, perform pre/post silicon verification and debug
Seniority
Senior, hands-on IC
