Sr Principal Verification Engineer
Core
Lead end-to-end pre-silicon design verification for complex digital SoCs, microprocessor-based designs, and AI/ML accelerators.
Role type
Sr Principal Verification Engineer (Digital Design)
Builds
Highly integrated SoC and subsystem solutions for the Intelligent Edge
Domain
Semiconductor / Digital Design Verification
Deliverable
production ML models | product features
Required skills
SoC/Subsystem architecture, Verilog/SystemVerilog, UVM, formal verification, NoC/interconnect verification, constrained-random verification, assertions, transaction-level modeling, power-aware verification (UPF), gate-level simulation (GLS), C/C++, Python/TCL/Shell
Preferred skills
Mixed-signal/analog verification (ADC/DAC/PLL/PHY), security and safety verification
Technologies
UVM, SystemVerilog, Verilog, Python, TCL, Shell, C, C++, SystemC, ARM, RISC-V, Tensilica, AXI, AHB, DMA, SVI3, I2C, SPI, Ethernet, UART
Responsibilities
Lead end-to-end SoC verification from planning to signoff; Architect and implement scalable UVM-based testbenches and DV flows; Define verification strategies and methodologies; Collaborate with architecture and design teams to align on requirements; Drive pre-silicon readiness with emulation, FPGA, and software teams; Perform performance verification and system-level analysis; Lead NoC/interconnect verification; Apply formal verification techniques for IP and subsystems.
Seniority
Sr Principal, hands-on IC with leadership
