Staff Design Verification Engineer – SoC and eFPGA
Core
Develop next-generation eFPGA technology and System-on-Chip (SoC) verification strategies, ensuring high-quality silicon delivery for heterogeneous processing and edge computing solutions.
Role type
Staff Design Verification Engineer (SoC and eFPGA)
Builds
End-to-end verification flows for eFPGA soft logic within SoCs, including RTL simulation, synthesis validation, and bitstream generation.
Domain
Semiconductor / Digital Hardware Design / eFPGA / SoC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM-based verification, SystemVerilog assertions, SoC architecture knowledge, AXI/AHB bus protocols, RTL debugging, simulation and waveform analysis, automation solutions, distributed compute environments, SystemC, Transaction-Level Modeling (TLM), C/C++, Python
Preferred skills
Silicon tape-out experience in advanced process nodes (N4, N5), Functional Safety (FuSA) verification, FPGA/programmable logic architecture knowledge, CI/CD regression automation
Technologies
UVM, SystemVerilog, Verilog, SystemC, Python, C/C++, AXI, AHB, RTL simulation tools, waveform analysis tools
Responsibilities
Partner with architecture, RTL, firmware, and software teams to define comprehensive verification strategies; Develop detailed verification plans covering feature interactions and system-level behavior; Design, implement, and maintain directed and constrained-random verification environments; Develop SystemVerilog assertions and functional coverage models; Debug simulation failures and collaborate with design teams to resolve issues; Analyze coverage metrics to enhance verification content; Build and support end-to-end verification flows for eFPGA soft logic.
Seniority
Staff, hands-on IC with strategic oversight
