Staff Engineer, Design Verification Engineering
Core
Develop and execute UVM-based verification environments for block-level and full-chip ASIC/SOC designs, ensuring thorough verification and coverage closure.
Role type
Staff Engineer, Design Verification Engineering
Builds
ASIC/SOC designs
Domain
Semiconductor / IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM, System Verilog, constrained-random testing, directed test cases, functional coverage analysis, assertion writing, IP/VIP integration, simulation debugging, waveform analysis, scripting for automation
Preferred skills
post-silicon verification support, evaluation and applications engineering collaboration
Technologies
UVM, System Verilog, design automation tools
Responsibilities
Create and implement verification plans and strategies; Write and analyze functional coverage, assertions, and metrics; Integrate and verify third-party and custom IPs/VIPs; Collaborate with design teams to review test plans and resolve issues; Automate simulation data analysis and model validation
Seniority
Staff, hands-on IC
