Senior DFT Engineer
Core
Designing and implementing DFT architecture, automation, and verification strategies to ensure high coverage, low power, and low test time for ASIC/SoC products.
Role type
Senior IC DFT Engineer (ASIC/SoC)
Builds
Verified silicon chips with robust test patterns and DFT infrastructure
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture and planning, Scan Insertion, Test Compression, ATPG, MBIST, LBIST, On-Chip Clock Control, Gate-level simulation with SDF, Silicon test bring up, Failure analysis, Scripting (Perl/Python/Tcl)
Preferred skills
Cadence and Synopsys DFT tools, IEEE 1149 and JTAG, Static Timing Analysis, Synthesis and DFT Insertion, Low Power Scan and UPF
Responsibilities
Define DFT specifications and architecture, Automate DFT flows, Generate ATPG patterns, Perform pre/post silicon verification and debug, Mentor junior team members
Seniority
Senior, hands-on IC
