Principal Engineer, Design Verification
Core
Lead design verification strategy and execution for Power Controller ICs, defining methodologies and mentoring a small team of engineers.
Role type
Principal Design Verification Engineer (Technical Lead)
Builds
Verification environments, testbenches, and validation flows for mixed-signal SoCs and power management ICs
Domain
Semiconductor / Analog & Mixed-Signal Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Formal Verification, Python, TCL, Perl, Shell, Coverage-driven verification, Mixed-signal verification, EDA tools, Testbench architecture
Preferred skills
Portable Stimulus Standard (PSS), SV-RNM modeling, ARM/RISC-V verification, Power management IC protocols (PMBUS, AVS, SVID), Emulation/FPGA prototyping, CI/CV pipelines, Git/Perforce, C/C++, SystemC
Technologies
JasperGold, VC Formal, Cadence, Synopsys, Mentor/Siemens, Python, TCL, Perl, Shell, Git, Perforce
Responsibilities
Define and implement DV strategy and plans; Mentor verification engineers; Architect scalable verification infrastructure; Conduct code and testbench reviews; Drive adoption of advanced methodologies (UVM, formal, AI/ML); Partner with design teams for mixed-signal integration; Represent verification in executive reviews.
Seniority
Principal, hands-on IC with leadership