Design Verification Engineer
Core
Confirm accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry before pattern generation/mask development; analyze equipment to establish operating data and conduct experimental tests to confirm devices meet specifications.
Role type
Design Verification Engineer (Analog/Mixed Signal)
Builds
Analog and mixed signal electronic equipment and hardware systems
Domain
Semiconductor / Analog and Mixed Signal Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog and mixed signal design fundamentals, design rule adherence, experimental test execution, software simulation, vendor capability review, BS degree in EE/ECE/CS
Preferred skills
2-5 years DV experience, SS/SOC/Post silicon DV, C based SOC DV, scripting (Python/Perl/Shell), DV flow ownership, UVM/System Verilog, AMS/GLS/PAGLS/CPF/UPF verification, digital design fundamentals, bus protocols (AXI, AHB, APB, CAN, Ethernet, I2C, SPI, UART, PSI5, Flexray), C based environment with ARM/DSP multi-processor systems, power aware simulations, Cadence tools (Xcelium/vManager/Formal applications/safety simulator), CDC DV, functional safety, ISO26262 guidelines
Technologies
Verilog, VHDL, C, Python, Perl, Shell, UVM, System Verilog, Xcelium, vManager, Formal applications, safety simulator
Responsibilities
Define verification strategy and plan to meet 100% spec to regression traceability; own DV environment including TB development, checkers, and coverage monitor definitions; collaborate with cross-functional teams (Architecture, RTL, PD, DFT, Systems, Analog, FW, application) for IP/Subsystem/SOC verification from spec definition to post silicon closure; perform final SoC DV signoff based on regressions, coverage metrics, and DV to spec traceability adhering to ISO26262 guidelines.
Seniority
Mid-level (2-5 years experience)