Senior DFT Engineer
Core
Design and implement Design-for-Test (DFT) architectures for complex ASIC/SoC products in automotive and industrial applications.
Role type
Senior IC DFT Engineer
Builds
ASIC/SoC chips with integrated DFT features
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features
Required skills
Scan architecture, ATPG, MBIST, JTAG, fault modeling (stuck-at, transition, at-speed), DFT tool integration, timing analysis, CDC analysis, low-power DFT flows
Preferred skills
Advanced node design, physical-aware DFT, test-related ECOs, UPF, low-power test strategies
Technologies
Synopsys DFT Compiler, TestKompress, Siemens Tessent
Responsibilities
Develop and integrate DFT architectures, implement and debug DFT logic, generate and analyze ATPG patterns, support at-speed and transition fault testing, collaborate with RTL/Physical Design/Test teams, address timing/CDC/low-power considerations, support test coverage analysis and silicon bring-up
Seniority
Mid-Senior, hands-on IC
