Sr Staff Engineer DFT
Core
Technical authority and strategic lead for end-to-end Design-for-Test (DFT) architectures in complex, high-performance SoCs, driving innovation in test methodology to ensure quality and minimize test cost.
Role type
Sr Staff Engineer DFT
Builds
Scalable, high-performance DFT flows and industry-leading DFT architectures for multi-die or chiplet-based designs.
Domain
Semiconductor manufacturing / SoC design / Test engineering
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture definition, ATPG/MBIST/LBIST strategies, silicon lifecycle management, RTL/Synthesis/Physical Design flow integration, post-silicon validation and debugging, TCL/Python/Perl scripting, EDA tool mastery (Synopsys/Cadence/Siemens), defect-oriented testing optimization, hierarchical scan and scan compression, mixed-signal test integration
Preferred skills
Automotive ASIL-D functional safety, In-System Test (IST), Volume Diagnostics and Yield Learning tools, technical conference participation, patented DFT innovations
Technologies
Synopsys TestMAX/DFTMAX, Cadence Modus, Siemens/Mentor Tessent, TCL, Python, Perl, 5nm/3nm nodes
Responsibilities
Define and own global DFT architecture including Hierarchical Scan and IEEE 1687 networks; Develop advanced strategies for defect-oriented testing and optimize pattern volumes; Lead integration of DFT requirements into RTL and Physical Design flows; Spearhead post-silicon validation and root-cause analysis of test failures; Architect and maintain scalable DFT flows using scripting languages; Provide technical mentorship and consult on verification and backend teams; Author comprehensive DFT specifications and strategy documents
Seniority
Sr Staff, hands-on IC with strategic lead responsibilities
