Sr Staff Engineer DFT
Core
Technical authority and strategic lead for end-to-end Design-for-Test (DFT) architectures in complex, high-performance SoCs, driving innovation in test methodology and silicon lifecycle management.
Role type
Sr Staff Engineer DFT (Technical Authority & Strategic Lead)
Builds
Scalable, high-performance DFT flows and industry-leading DFT architectures for multi-die or chiplet-based designs.
Domain
Semiconductor manufacturing / SoC Design / Test Engineering
Required skills
DFT architecture design, ATPG/MBIST/LBIST strategies, Silicon bring-up & debugging, EDA tool mastery (Synopsys/Cadence/Siemens), Scripting (TCL/Python/Perl), Cross-functional integration, Technical documentation, Mentorship
Preferred skills
Automotive ASIL-D functional safety, Yield analysis tools, Patented DFT innovations
Technologies
Synopsys TestMAX/DFTMAX, Cadence Modus, Siemens/Mentor Tessent, TCL, Python, Perl, 5nm/3nm nodes
Responsibilities
Define global DFT architecture including Hierarchical Scan and Compressed ATPG; Develop defect-oriented test strategies; Integrate DFT requirements into RTL and Physical Design flows; Spearhead post-silicon validation and root-cause analysis of test failures; Architect and maintain scalable DFT automation flows; Provide technical mentorship to junior and senior engineers.
Seniority
Sr Staff, hands-on IC with strategic leadership
