Senior Staff, DFT Engineering
Core
Lead DFT strategy and implementation for complex SoCs, driving architecture and methodology for scan, BIST, and boundary scan to ensure robust test coverage.
Role type
Senior Staff DFT Engineering Lead (IC)
Builds
Complex SoCs with robust test coverage
Domain
Semiconductor / Hardware Engineering
Required skills
DFT Architecture, Scan insertion, ATPG, MBIST, LBIST, JTAG, Verilog/System Verilog, TCL, Perl, Python, Test Coverage Analysis
Preferred skills
Technical leadership, Budget management, Project financials
Technologies
Synopsys, Mentor Tessent, Cadence Modus
