Senior DFT Engineer
Core
Define and implement DFT architecture for SoCs to optimize test cost and achieve high coverage, covering scan, MBIST, and post-silicon bring-up.
Role type
Senior DFT Engineer
Builds
Production-ready SoC test architectures and flows
Domain
Semiconductor / Digital IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> product features (DFT flows, test architectures)
Required skills
DFT architecture definition, SCAN implementation (partition, compression, at-speed, IR, low power), MBIST, JTAG boundary scan, hierarchical scan, ATPG flow implementation, pattern simulation, post-silicon bring-up support, failure analysis, Perl/Python/TCL scripting, HDLs
Preferred skills
Tessent DFT tools, UPF/CPF for low power, Cadence Genus/Tempus, timing closure, physical design
Technologies
Tessent, UPF, CPF, Cadence Genus, Cadence Tempus, ATE
Responsibilities
Define DFT architecture and test requirements, develop SCAN and MBIST insertion flows, implement ATPG flows, simulate patterns, support post-silicon bring-up and failure analysis, collaborate with physical design and test engineering teams, guide new team members on DFT methodology
Seniority
Senior, hands-on IC
