Staff Engineer – DFT Engineering
Core
Design and implement Design for Testability (DFT) features for complex integrated circuits to ensure efficient manufacturing testing and yield.
Role type
Staff DFT Engineer (VLSI/ASIC)
Builds
Production-ready ICs with embedded test structures (scan chains, MBIST, LBIST) and high-quality ATPG test patterns.
Domain
Semiconductor / VLSI Design / Analog & Digital ICs
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT methodologies (LBIST, ATPG, MBIST, Boundary Scan, JTAG), RTL/Netlist DFT DRC, Scan compression, Low power DFT, Perl/Tcl/Python scripting, ASIC design flow, STA constraints, Debugging test failures
Preferred skills
Mentorship of junior engineers, Collaboration with verification and physical design teams, Analog/Phy DFT expertise
Technologies
Cadence, Siemens EDA tools, RTL, Netlist, SDF
Responsibilities
Design and implement DFT features (scan chains, compression, BIST), Conduct DFT DRC checks in RTL/Netlist, Generate manufacturing ATPG test patterns, Validate DFT structures/patterns, Collaborate with verification and physical design teams, Analyze and debug test failures, Provide guidance to junior engineers
Seniority
Senior, hands-on IC
