Staff Engineer, Timing
Core
Ensure timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and high-performance computing devices.
Role type
Staff Timing (STA) Engineer (IC)
Builds
GPU Intellectual Property (IP) for mobile, automotive, and custom market segments
Domain
Semiconductor / ASIC Design / High-Performance Computing
Deliverable
production ML models | product features
Required skills
Timing analysis, ASIC design flows, STA tools (PrimeTime, Tempus), Clock tree synthesis (CTS), Multi-voltage/multi-clock design, Scripting (Tcl, Perl, Shell, Python), Timing constraints, UPF, Low-power techniques
Preferred skills
FinFET process nodes (5nm+), Synthesis, Full chip implementation, Reliability/Signal integrity/Noise closure
Technologies
PrimeTime, Tempus, Tcl, Perl, Shell, Python
Responsibilities
Execute hands-on timing analysis at top level and debug constraints for complex GPU IPs; Collaborate with RTL, physical design, and SoC teams to resolve timing issues; Identify tool bugs and influence flow/methodology enhancements; Support timing closure and signoff readiness via timing budgeting and derating; Take initiative on moderate-to-complex projects and document analysis results
Seniority
Senior, hands-on IC
