STD Cell QA Engineer
Core
Developing and verifying high-performance standard cell libraries for semiconductor chips, focusing on power optimization, clock cells, and circuit reliability.
Role type
Senior IC standard cell design and verification engineer
Builds
Standard cell libraries for System LSI, Memory, and Foundry products
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | infrastructure
Required skills
Standard cell library QA methodologies, test plan development, regression testing, post-layout verification, high-performance flip flop design, latch design, multibit flip flop design, voltage level shifter design, power optimization cell design, clock cell design, CMOS device characteristics, design rule compliance, latch-up analysis, electro migration analysis, digital circuit simulation, PPA optimization, statistical variation analysis
Preferred skills
Environment development, post-layout netlist extraction
Technologies
Standard cell libraries, CMOS, digital circuit simulation tools
Responsibilities
Develop test plans and execute regression testing for standard cell libraries, design high-performance flip flops, latches, and clock cells, optimize power consumption and performance of standard cells, analyze statistical variations in circuit behavior, ensure compliance with design rules and reliability standards
Seniority
Senior, hands-on IC
