Design Verification Engineer
Core
Design Verification Engineer responsible for verifying Foundry IP and high-speed interface components for Samsung's System LSI, Memory, and Foundry solutions.
Role type
Design Verification Engineer (IP/Sub-system)
Builds
Reusable DV components and verification environments for High Speed Interfaces, Security, and Memory Technologies.
Domain
Semiconductor / Foundry / System LSI / Memory / High Speed Interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM (SystemVerilog), Formal Verification, Coverage Metrics, Python, Perl, PCIe, Gigabit Ethernet, UNIPRO, MPHY, LPDDR, HBM, AMBA Bus protocols (APB, AHB, AXI)
Preferred skills
Experience with automation scripting and tools
Responsibilities
Design and implement reusable DV components for High Speed Interfaces, Security, and Memory Technologies; Create and utilize verification components using industry-standard methodologies (e.g., SV-UVM, Formal); Define and track key coverage metrics to ensure thorough verification and identify potential design flaws.
Seniority
Mid-Senior (4-8 years experience)
