SMTS-Verification IP role
Core
Developing comprehensive verification IPs for high-speed interfaces (PCIe, USB, Ethernet, DDR, CXL) to help design teams find bugs faster using Questa RTL simulation.
Role type
Verification IP Engineer
Builds
Questa verification IP components for PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5, and CXL protocols
Domain
Electronic Design Automation (EDA) / Chip Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Assertions, Coverage, Test plan design, BFM design, Debug, Logger, Standard bus protocols (PCIe, USB, SATA, NVMe, Flash, DIMM)
Preferred skills
Experience with Questa RTL simulation, Knowledge of coherency protocols
Technologies
Questa RTL, System Verilog, UVM, PCIe, USB, Ethernet, DDR, CXL
Responsibilities
Specify, implement, test, and enhance verification components; Work on SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger; Collaborate with TMEs, Field AEs, or customers to deploy or resolve issues
Seniority
Mid-level IC
