SMTS-Verification IP
Core
Developing comprehensive verification IPs for high-speed interfaces and coherency protocols to help design teams find bugs faster using Questa RTL simulation.
Role type
Verification IP Engineer
Builds
Verification components for PCIe, USB, Ethernet, DDR, and CXL protocols
Domain
Electronic Design Automation (EDA) / Chip Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Assertions, Coverage, Test plan design, BFM design, Debug, Logger, Standard bus protocols (PCIe, USB, SATA, NVMe, Flash, DIMM)
Preferred skills
Experience with Questa RTL simulation, Knowledge of coherency protocols like CXL
Technologies
Questa RTL, System Verilog, UVM, PCIe, USB, SATA, NVMe, Flash, DIMM, CXL
Responsibilities
Specify, implement, test, and enhance verification components; Work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger; Collaborate with TMEs, Field AEs, or customers to deploy or resolve issues
Seniority
Mid-level, hands-on IC
