Senior Director, Silicon Architecture and Design Engineering (PCIe)
Core
Lead the PCIe Center of Excellence to define architecture, roadmap, and delivery of hard/soft IP for high-speed interconnect technologies across programmable device portfolios.
Role type
Senior Director, Silicon Architecture and Design Engineering (PCIe)
Builds
Multi-generation PCIe and adjacent coherent interconnect (CXL) IP, controllers, and subsystems for FPGA, ASIC, and SoC products.
Domain
Semiconductor / High-Speed Interconnect / Silicon Design
Required skills
PCIe architecture and protocol (Gen4/Gen5), PHY/SerDes integration, SoC integration, silicon engineering leadership, cross-functional program execution, IP reuse strategy, verification and compliance strategy, customer enablement
Preferred skills
PCIe Gen6/Gen7 architectures, CXL.io/cache/mem, SR-IOV/ATS/PASID/IOMMU, UCIe, silicon security, FPGA architectures, performance modeling for AI/HPC
Technologies
PCIe, CXL, FPGA, ASIC, SoC, SerDes, PHY, RTL, DFT, emulation
Responsibilities
Lead and mentor a large silicon engineering organization; own end-to-end delivery of complex silicon programs; set technical direction for PCIe and adjacent interconnects; drive scalable design methodologies and automation; establish verification, validation, and compliance strategies; represent silicon engineering in executive reviews and partner with ecosystem organizations
Seniority
Senior Director, strategic leadership and large-scale organization management
