Director Post-Si Electrical Validation Engineering
Core
Lead the development, bring-up, and validation of ASIC SerDes and PCIe PHY products for rack-scale AI infrastructure.
Role type
Director, Post-Si Electrical Validation Engineering
Builds
High-speed connectivity and memory products for cloud service providers, server manufacturers, and networking OEMs
Domain
Semiconductor / High-Speed Interconnects (PCIe, SerDes)
Required skills
ASIC SerDes/PHY validation, Signal Integrity, Power Integrity, PVT characterization, Debug (silicon/PCB), Validation Automation, Cross-functional leadership, Python scripting, Lab equipment operation (Oscilloscope, BERT, VNA)
Preferred skills
SoC Debug for PCIe5/6 or PAM4 Ethernet, PHY design blocks (PLL, DFE, Tx EQ, FFE, CDR), Python for bench automation, Startup experience
Technologies
PCIe Gen 3+, PCIe5, PCIe6, PAM4, CXL, Ethernet, NVLink, UALink, Python, Git, BERT, Oscilloscope, VNA
Responsibilities
Define validation plans, coverage goals, and risk assessments for high-speed ASIC/PHY IP; Direct ASIC power-on bring-up, debug, and performance optimization; Partner with ASIC, firmware, and manufacturing teams to deliver robust products; Build and mentor a high-performing engineering team; Drive products from concept to mass production.
Seniority
Director, hands-on technical leadership
