Lead Logic Design - PCIE IP/Subsystem Engineer
Core
Lead the development of complex connectivity IPs/subsystems including micro-architecture, RTL implementation, integration, and silicon bring-up.
Role type
Lead IC logic design engineer (PCIe IP/Subsystem)
Builds
Custom connectivity solutions integrating PCIe, CXL, Ethernet, NVLink, and UALink technologies
Domain
Semiconductor / High-speed connectivity infrastructure
Deliverable
production ML models | product features
Required skills
RTL design (SystemVerilog/Verilog), PCIe architecture and protocol, micro-architecture design, high-speed data path design, flow control and arbitration, error handling, simulation and timing analysis, silicon bring-up, post-silicon debugging
Preferred skills
Switching silicon experience, end-to-cycle ownership from concept to silicon production
Technologies
SystemVerilog, Verilog, PCIe, CXL, Ethernet, NVLink, UALink, UCIe
Responsibilities
Lead RTL/microarchitecture development for complex connectivity IP/subsystems; Translate specifications into robust hardware architecture; Design high-performance and scalable logic for controllers/subsystems; Work across connectivity IP layers including Transaction, Data Link, and Physical interface integration; Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability; Drive performance, latency, area, and power optimization; Collaborate with verification teams to develop verification strategies and debug complex failures; Work with SoC integration and physical design teams; Lead technical reviews and mentor senior engineers; Support post-silicon debug and root-cause analysis
