Senior Physical Design Engineer
Core
Develop large mixed-signal SoC ASICs targeting advanced technology nodes to optimize performance, power efficiency, and area for Ciena's WaveLogic optical fiber transmission solutions.
Role type
Senior IC physical design engineer (ASIC/SoC)
Builds
Production ASICs for high-speed optical networking
Domain
Telecommunications / Semiconductor Physical Design
Deliverable
production ML models | product features
Required skills
ASIC physical digital design, timing closure, Place&Route tools, backend flow automation scripting, UPF, SOCV/POCV concepts, Static Timing Analysis (STA), cross-functional collaboration
Preferred skills
Physical verification (Calibre), power integrity (EMIR), physical synthesis, RTL-to-GDS flow, multiple power domains
Technologies
EDA vendor tools, Formality, Conformal, Calibre, UPF, SOCV/POCV
Responsibilities
Define physical architecture and build netlist-to-GDSII flows; Create floorplans, power grids, and clock distribution networks; Fine-tune EDA tool settings for PPA optimization; Generate and implement timing and functional ECOs; Conduct Place & Route trials and correlate with RTL; Run STA and debug timing constraints; Write scripts to automate backend tasks; Collaborate with analog and RTL designers.
Seniority
Senior, hands-on IC