THW Client Co-op (January 2027 - Rochester, NY)
Core
Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation within Ciena's WaveLogic coherent engine chipsets.
Role type
Junior IC ASIC design and verification engineer (co-op)
Builds
Digital ASIC products and FPGA-based validation environments
Domain
Optical networking and high-speed connectivity
Required skills
SystemVerilog, Verilog, VHDL, Python, ASIC/FPGA development, IEEE 802.3/ITU/OIF standards
Preferred skills
OTN/Ethernet/Optical Networking standards, Linux environment, debugging
Responsibilities
Design and verify digital blocks, cores, and subsystems; Collaborate with design and verification engineers; Implement digital designs; Verify digital designs using UVM methodologies; Develop and enhance prototype and development automation solutions; Apply communications standards knowledge
Seniority
Student co-op (Junior)
