ASICS Design Engineer, Senior to Staff
Core
Design and implement RTL, synthesis, and timing closure for Ethernet switch datapath and control logic within merchant silicon SoCs.
Role type
Senior ASIC Design Engineer (Networking/Switching)
Builds
Ethernet switch ASICs (merchant silicon)
Domain
Semiconductor / Networking ASICs
Required skills
RTL coding, ASIC design flow (FE), timing closure, synthesis, Ethernet switching concepts (L2/L3, QoS), packet processing pipelines, buffer management, AXI/NoC, PCIe, high-speed interfaces, system-level debugging, C/C++/Tcl/Perl scripting
Preferred skills
Merchant silicon or switching ASIC experience (Broadcom/Marvell/Realtek/MTK), micro-architecture design, power optimization, mentoring
Technologies
RTL, Synopsys/Cadence flows, Ethernet, VLAN, TCP/IP, AXI, NoC, PCIe
Responsibilities
Implement RTL design, synthesis, and timing closure for networking datapath/control logic; Lead design and delivery of key subsystems in Ethernet switch ASICs; Own micro-architecture and RTL design of networking blocks (forwarding engine, parser, traffic manager); Drive subsystem integration, performance tuning, and power optimization; Debug functional and performance issues across design, DV, and validation teams; Mentor junior engineers and guide best engineering practices
Seniority
Senior to Staff, hands-on IC
