Verification Engineer - Test Automation
On-site
Core
Develop and manage verification environments for high-end router FPGA designs using SystemVerilog and UVM.
Role type
Senior IC verification engineer (ASIC/FPGA)
Builds
Verification environments, testbenches, and test cases for high-end networking hardware
Domain
Networking hardware / FPGA design
Required skills
SystemVerilog, UVM, Object-Oriented Programming, constrained-random verification, coverage analysis, PCIe, Ethernet, I2C, SPI, MDIO
Preferred skills
Masters degree in Electrical Engineering
Technologies
SystemVerilog, UVM, Ethernet, PCIe, FPGA
Responsibilities
Manage verification of complete FPGA designs for high-end router products, define verification scenarios with design engineers, craft test plans and regression setups, identify coverage measures for corner cases, create object-oriented testbench frameworks and BFMs
