ASIC Design Verification Engineer, up to Sr. Staff
Core
Develop testbenches and test cases for Ethernet switch verification at module, subsystem, and system levels, collaborating with architecture and design teams.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Ethernet switching ASICs
Domain
Networking / Semiconductor
Required skills
System Verilog, UVM, SVA, Coverage-driven methodology, Emulation/FPGA validation, Ethernet protocols (VLAN, TCP/IP, TSN), Packet classification/forwarding, Buffer management, QoS, C/C++ scripting, Tcl, Perl
Preferred skills
Merchant silicon or switching ASIC experience (Broadcom, Marvell, Realtek, MTK), Micro-architecture definition, RTL design knowledge, Pre/post-silicon debugging, Mentoring
Technologies
System Verilog, UVM, SVA, C, C++, Tcl, Perl, Ethernet, VLAN, TCP/IP, TSN
Responsibilities
Develop testbenches and test cases for Ethernet switch verification; Collaborate with Architecture and Design teams on micro-architecture and RTL design; Support pre-silicon and post-silicon debugging; Mentor junior engineers
Seniority
Senior to Staff, hands-on IC
