Principal/Team Lead, Digital Verification Engineer (FEC)
Core
Develop verification strategies, test plans, and testbenches to simulate and validate Forward Error Correction (FEC) functional blocks and subsystems for high-speed connectivity modems.
Role type
Principal/Team Lead Digital Verification Engineer (FEC)
Builds
Wavelogic modem family products (Forward Error Correction IP)
Domain
Telecommunications / High-speed networking / Digital Verification
Deliverable
production ML models | product features
Required skills
Digital verification strategy, Functional coverage, Formal verification, System Verilog UVM, C++, Debugging complex failures, Team mentorship, Technical leadership
Preferred skills
Forward Error Correction (FEC) domain expertise, DSP background, Python, Bash, Jira, GIT
Technologies
System Verilog, UVM, C++, C, Python, Jira, GIT
Responsibilities
Develop verification and functional coverage test plans; Create testbench environments, agents, and test scenarios; Perform coverage-driven verification and debug failures; Mentor and supervise junior verification engineers; Communicate verification progress and risks to stakeholders
Seniority
Principal, hands-on IC with team leadership
