Mixed Signal Design Engineer
Core
Designing high precision Sigma-Delta DAC and ADC for control and monitoring, and creating SystemVerilog and IBIS-AMS models for high-speed SerDes IP.
Role type
Mixed Signal Design Engineer
Builds
High-speed DAC and ADC analog macros for coherent fiber-optic product solutions
Domain
Telecommunications / High-speed connectivity / Optical fiber transmission
Deliverable
production ML models | product features
Required skills
CMOS and BiCMOS design, Cadence Virtuoso/Xcelium/AMS, Synopsys VCS/StarRC, Siemens Questa/Formal/Calibre/SymphonyAMS/AFS, SystemVerilog, VerilogAMS, VerilogA, Matlab/Simulink, C/C++, Python
Preferred skills
UVM, Git, Gradle, Google Tests, RF and Signal Integrity tools, DSP and digital design, AI tools for automation
Responsibilities
Designing high precision Sigma-Delta DAC and ADC for control and monitoring, Designing SystemVerilog models for various analog macros, Designing IBIS-AMS models for high-speed DAC and ADC based SerDes IP, Creating Design Specification Document, Interacting with and providing support to system, analog, digital, DSP, signal integrity, hardware, firmware, and analog lab bring-up teams
Seniority
Individual Contributor