Senior Analog Layout Engineer
Core
Designing high-speed analog layouts for optical fiber transmission solutions, specifically DAC/ADC SERDES and optical-line-facing circuits in deep-submicron CMOS/BiCMOS.
Role type
Senior IC analog layout engineer
Builds
High-speed analog macros (DAC, ADC, PLL, SERDES) for coherent fiber-optic product solutions
Domain
Telecommunications / Semiconductor IC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Custom analog and mixed-signal layout design, deep-submicron CMOS device knowledge (Finfet), floor planning, placement and routing, DRC/ANT/LVS/PERC/EM/IR verification, layout tools (Cadence Virtuoso, Siemens Calibre, Ansys Totem), parasitic minimization, RF shielding, scripting (PERL/SKILL)
Preferred skills
Semiconductor manufacturing process familiarity, advanced process effects (LOD, OSE, WPE), guard rings/DNW/PN junctions
Technologies
Cadence Virtuoso, Siemens Calibre, Ansys Totem, CMOS, BiCMOS, Finfet
Responsibilities
Conduct layout feasibility studies with senior designers, create layouts for assigned analog blocks, perform verification checks (DRC, ANT, LVS, PERC, EM, IR), investigate new layout tool features, provide status updates and share experiences
Seniority
Mid-level IC engineer (1-5 years experience)
