THW Client Co-op
Core
Digital ASIC design and verification of client protocol mapping IP for Ciena's Wavelogic coherent engine Chipsets.
Role type
Co-op Digital ASIC Design and Verification Engineer
Builds
Wavelogic ASICs and FPGA-based validation environments
Domain
Optical networking and digital hardware design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Verilog, VHDL, Python, RTL design, digital block design, ASIC development, FPGA development
Preferred skills
OTN standards, Ethernet standards, Linux environment, debugging, problem solving
Technologies
System Verilog, UVM, Verilog, VHDL, Python, Linux
Responsibilities
Perform RTL design and verification of digital blocks, cores, and subsystems; Implement and verify digital designs; Work within the ASIC IP team on design and verification of complex digital blocks and subsystems.
Seniority
Co-op (Undergraduate)
