ASIC Digital Designer (HSE-TS-IMS-2026-189-GRAE)
Core
Design, simulate, and verify the digital architecture of next-generation ASIC front-ends for radiation monitoring systems at particle accelerators.
Role type
Junior ASIC Digital Designer
Builds
ASIC front-end chips for safety-critical radiation monitoring
Domain
Particle physics instrumentation / Digital ASIC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
VHDL, Verilog, SystemVerilog, RTL design, floorplanning, physical design preparation, open-source EDA flows (Yosys, OpenROAD, LibreLane), Linux scripting (Python, Bash), Git, CI/CD pipelines
Preferred skills
Post-tapeout prototype bring-up, hardware debugging, SoC submodule development, RISC-V architecture, mixed-signal integration
Technologies
Yosys, OpenROAD, LibreLane, Python, Bash, Git
Responsibilities
Design and simulate digital architecture for ASIC front-ends, prepare RTL designs for tapeout including floorplanning, support post-fabrication bring-up and validation, collaborate with analogue and verification teams
Seniority
Junior (0-2 years experience)
